`timescale 1ns/100ps
/*************************************************************
 This file is for simulate eXordiumCore, remember to add  "IRAM" file  in the "CoreSIM" file!
**************************************************************/
module Core_test(

);
//----------------Global signals-----------------
    reg rst;
    reg clk;

//----------------IRAM signal--------------------
    wire [31:0] inst;
	wire [31:0]	instAddr;
//----------------Core signal---------------------
    wire [31:0] pc;
	wire [31:0] Master_WB_ADRo;
	wire [31:0] Master_WB_DATi;
	wire [31:0] Master_WB_DATo;
	wire		Master_WB_WEo;
	wire		Master_WB_CYCo;
	wire		Master_WB_ACKi;
	wire [03:0]	storeBankSel;

//---------------------eXordiumCore-------------------------
    eXordiumCore                    eXordiumCore
    (
        .clk                        (clk),
        .rst                        (rst),
	
        .inst                       (inst),
        .pc                   		(pc),				
        .WB_ADRo                    (Master_WB_ADRo),
        .WB_DATo                    (Master_WB_DATo),
        .WB_DATi                    (Master_WB_DATi),
        .WB_WEo                     (Master_WB_WEo),
        .WB_CYCo                    (Master_WB_CYCo),
        .WB_ACKi                    (Master_WB_ACKi),
        .storeBankSel               (storeBankSel)
    );
	assign	Master_WB_ACKi = 1'b1;


//---------------IRAM----------------------
IRAM            IRAM
	(
		.address        (pc[13:2]),
		.clk            (clk),
		.q              (inst)
	);


initial begin
    rst	    =   1'b1;
    clk   	=   1'b0;

#100
    rst     =   1'b0;
end

always begin
    #10 clk = ~clk;   //50MHz clock
end


endmodule